The students are encouraged to add features to the basic simulator. Some of the features added by the students or suggested by the instructor include:
In addition, the simulator can be modified to simulate other microcoded machines. Some of the possible changes include:
A survey was distributed on the last day of class. Students indicated that they thought the simulator project enhanced their understanding of microprogramming and how computers worked in general. They also found the project interesting and enjoyed working on it. The latter may be the most important benefit in that students learn best when working on something they enjoy.
Other instructors are encouraged to use this simulator project. The following are available via anonymous ftp [9]. Essentially everything is available except for the simulator source code which the students should write.
This appendix provides an overview of the Mic-1 and Mac-1 from Tanenbaum's book. Refer to Figure 1 in the text during the discussion.
The Mic-1 instruction cycle consists for four subcycles. On the first subcycle the microprogram counter (MPC) picks out one of the 256 possible words in the control store, and this value is stored in the microinstruction register (MIR). On the second subcycle one of the sixteen registers is stored in the A latch and one in the B latch. The A and B fields of the MIR determine which registers are chosen. The AMUX bit in the MIR determines whether the left input to the ALU comes from the memory buffer register (MBR) or the A latch. The ALU bits control the ALU functions (add, and, pass A, complement A) and the SH bits control the Shifter which can shift one bit to the left or right, or not shift at all. The result of this combinational logic is assumed to be available by the start of subcycle 4. In the meantime, during subcycle 3 the low 12 bits of the B latch are stored in the memory address register (MAR) if the MAR bit of the MIR is set.
On subcycle 4, the result from the Shifter is stored in the MBR if the MBR bit of the MIR is set. The result is also stored in the register specified by the C field of the MIR if the ENC (enable C bus) bit is set. Additionally on subcycle 4, the COND bits of the MIR along with the negative (N) and zero (Z) flags of the ALU determine the next address to be loaded into the microprogram counter (MPC). The options are to increment the MPC or to use the branch address stored in the ADDR field of the MIR. The possibilities are branch never, branch always, branch on zero, or branch on negative.
A Mic-1 cycle can also initiate either a read or a write operation as determined by the RD and WR bits of the MIR. Main memory is accessed by writing the address in the MAR. For a read, the RD control line is activated for two Mic-1 cycles. The value read is then available in the MBR and can be moved into one of the sixteen Mic-1 registers. For a write, the value to be written is moved to the MBR, and the WR line is activated for two Mic-1 cycles. This stores the value in memory.
Tanenbaum gives a control store for the Mic-1 (just 79 words) which implements a simple assembly language instruction set called the Mac-1. The 23 instructions of the Mac-1 include load, store, add, and subtract instructions for a simple accumulator machine using direct and stack addressing. Other instructions include push, pop, call, return, and jump. Four of the Mic-1 registers represent the program counter (PC), accumulator (AC), the stack pointer (SP), and the instruction register (IR) of the Mac-1 machine. Two other registers are used for scratch registers. Five registers hold constants and the remaining five of the sixteen Mic-1 registers are not used by the control store which implements the Mac-1.
The basic instruction cycle for a Von Neumann machine such as the Mac-1 consists of instruction fetch, increment program counter, decode instruction, and execute instruction. The Mac-1 instruction cycle is started with the execution of microinstruction zero. The instruction whose address is contained in the PC is read into the instruction register, the PC is incremented, and the instruction is decoded. The decoding takes a long time on the Mic-1 because it is done by examining the bits of the instruction one at a time. The decoding is not described here.
As an example of instruction execution,
consider the Mac-1 POP instruction which removes the memory value at the
top of the stack and puts it into the accumulator (AC).
POP can be described functionally as:
ac := m[sp]; sp = sp+1;
The Mac-1 POP is implemented by three instructions in the Mic-1 control store:
mar := sp; sp := sp + 1; rd;
rd;
ac := mbr; goto 0;
The first of these instructions does two operations. It starts the memory read necessary to obtain the word on the top of the stack, and it increments the stack pointer. Since memory operations take two Mic-1 cycles, the next instruction just waits for the read to complete by keeping the RD line active. In the third instruction, the result read from memory is moved from the MBR into the AC. The instruction then transfers control ( goto 0) to the part of the microprogram which starts the next Mac-1 instruction cycle.
Let us look in detail at how the first of these instructions is executed in a single cycle of the Mic-1 machine. Since the Mic-1 is also a Von Neumann machine, the instruction cycle of the Mic-1 also consists of the operations of (micro)instruction fetch, increment (micro)program counter, decode (micro)instruction, and execute. Here is how this is done on the four subcycles of the Mic-1.
On the first subcycle, the instruction pointed to by the MPC is moved from the control store into the MIR. Since each collection of bits in the control store has an independent control function, the instruction is already decoded. A control store with this property is called horizontal. The next three subcycles perform the execution and the incrementing of the MPC. The microinstruction: mar := sp; sp := sp + 1; rd; is given below:
On subcycle 2, the register in the A field of the MIR is moved into the
A latch and the register in the B field is moved into the B latch.
Register 6=
has the constant one, and register 2=
is the SP.
The AMUX field of 1 selects the A latch as the left input of the ALU.
The ALU field of 0 specifies that the ALU should add its two inputs,
and the SH field of 0 indicates that the Shifter should not shift.
After some delay determined by the speed of this combinational logic,
the output of the Shifter will be SP+1.
On subcycle 3, since the MAR field of the MIR is 1, the contents of the B latch (the SP register) is stored in the MAR. Since the RD field is one, a read cycle is started.
On subcycle 4, since the ENC (enable C bus) field of the MIR is one, the Shifter output is stored in the register in the C field of the MIR. This is register 2, which is the SP register. Thus, the SP register has been incremented. Because the MBR field is 0, the Shifter output is not stored in the MBR. The COND field of 0 indicates that no jump is to be performed and so the left input of the Mmux is used to load the new value of the MPC. This increments the MPC. The ADDR field is not used by this microinstruction since no branch occurred.