CS 2734
Computer Organization II
Review for Exam 2, Spring 1999 (April 23)
- Clocks -- the basic idea of how clocked circuits work,
with a latched state element feeding into combinational logic,
which in turn feeds in a loop back to the latched state element for
the next clock cycle.
- Section B.4, pages B-18 to B-21.
- Chapter 5, pages 341-343.
- Memory elements (Sections B.5, B-21 to B-25). You should be able to
explain how the following three items work.
- Cross-coupled NOR gates that store an internal value.
- The D latch, which responds to asserted clock signal.
- The D flip-flop, which responds to a falling clock signal.
- Datapath Overview (Sections 5.1 and 5.2). Rough organization
and components, including Instruction Memory, Register File,
ALU, and Data Memory.
- Single-cycle Implementation (Section 5.3) Note: Labs 7 through 11
are relevant here. Questions might involve knowledge gained by
simulating the single-cycle machine.)
- Above components, plus Control and ALU control.
- Implementation of basic instructions.
- R-type (add, sub, etc.)
- lw and sw
- beq
- j
- Be able to trace through a single-cycle diagram for
each instruction.
- Understand control signals and which need to be asserted
for a given instruction.
- Why single-cycle implementation is not used.
- Multi-cycle Implementation (Section 5.4)
- Above components, plus Instruction register.
- Use of a register between each pair of components,
so latch between clock cycles
- Implementation of basic instructions.
- R-type (add, sub, etc.)
- lw
- sw
- beq
- j
- Five cycles for instructions (only lw needs all five).
- Be able to trace through a single-cycle diagram for
each instruction.
- Understand control signals and which are needed.
- Finite state machine for control (Section 5.5).
- Advantages of multi-cycle implementation.
- Exceptions (in multi-cycle implementation, Section 5.6).
- Pipelined Implementation (Chapter 6)
- Overview (Section 6.1, includes especially discussion of
hazards).
- Pipelined datapath (Section 6.2, ignores hazards).
- Pipelined control (Section 6.3, makes use of extra latched
register storage between pipeline stages to pass along control
information. Ignores hazards.)
- Data hazards and forwarding (Section 6.4).
You should understand how forwarding work, with the Forwarding Unit
and extra control and data lines.
This applies to dependencies between register result of one
instruction and the use of that new register value in subsequent
instructions.
- Data hazards and stalls (Section 6.5).
In case of a dependency involving a lw instruction,
the machine must stall for one instruction. Use of the
Hazard Detection Unit.
- Branch hazard (Section 6.6). In case of a branch,
if the branch is taken (in one simple implementation),
must stall and wipe out the start of the next instruction.
(Also need to move branch handling into step 2 of pipeline.)
- Exceptions (Section 6.7).
Revision Date: 4/19/99