CS 2734 Computer Organization II

Lecture 41: RISC versus CISC - 4/28/97

Read Tanenbaum p. 436-443 (Section 8.1.2)

In this lecture we compare RISC (reduced instruction set computers) and CISC (complex instruction set computers).

Complexity of Instruction Set:
- Number of instructions:
  - A CISC architecture has hundreds of instructions with a wide variety in number of cycles that it takes to execute them.
  - A RISC instruction set contains relatively few instructions. Designed so that pipeline can produce one or more results per instruction cycle.
- Instruction encoding:
  - A CISC instruction set is more highly encoded:
    - Irregular
    - Expanding opcodes
    (Take a brief look at Figure 5-22 of Tanenbaum. Intel 8088 machines have instructions ranging from one to 19 bytes long.
  - RISC instruction sets are designed to require a minimum of decoding:
    - Regular
    - Few formats
    - Orthogonal operands.
    Sparc architecture has all instructions occupying exactly one word --- makes pipelining more convenient.
- Supported operand types:
  - A CISC instruction set supports a variety of memory addressing modes:
    - Immediate - operand in instruction
    - Register - operand in register
    - Register direct - address of operand in register
    - Direct - address of operand in instruction
    - Indirect - pointer to address of operand in instruction
    - Stack - address of operand implied and contained in a register.
    - Indexed - address computed as a base + size*(index register)
    (Take a brief look at Figure 5-5 of Tanenbuam.)
  - A RISC architecture is load and store:
    - Only instructions that are allowed to address memory are the load and the store.
    - Remaining instructions only use register and immediate addressing.
Processor architecture:
- Registers:
  - A CISC architecture:
    - Doesn't have register windows (look at Figure 5-9 of Tanenbaum).
    - On-chip cache hides memory latency.
  - A RISC architecture:
    - Register windows for fast context switching.
    - Cache too.
- Control:
  - CISC machines sometimes use microcode control. (The Pentium has an interesting approach.)
  - RISC machines always use hardware control.
- Execution:
  - Pentium uses out of order execution.
  - DEC Alpha uses pipelining with multiple pipelines.
SKILL: You should understand the basic characteristics of RISC versus CISC

Revision Date: 4/25/97