CS 2734
Computer Organization II
Lecture 39: Bus Arbitration
- 4/23/97
Read pages 111-124 (Sections 3.4.1 - 3.4.5)
and pages 137-141 (Section 3.6.1) of Tanenbaum
- Bus arbitration:
- Centralized versus decentralized.
- Diasy chaining.
- Extra bus busy line allows arbiter to determine next request
while current bus transaction completes.
- A typical DMA controller: (Diagram handed out in class).
- Processor stores initial values in address, command and count
registers.
- DMA controller has to wait for external device to be ready and processor
to be idle.
- External device synchronizes through 3 lines:
- I/O port asserts
TRANSFER REQUEST when ready.
- DMA controller asserts
TRANSFER ACK to tell
port to go ahead with transfer on bus.
-
READ/WRITE L when asserted to READ
transfer is from memory to I/O. (Note, when processor asserts
READ/WRITE L for this device, the transfer is in
the other direction.
- Processor synchronizes through two lines:
- Controller asserts
HALT when the device
is ready.
- Processor relinquishes bus by asserting
HALT ACKNOWLEDGE.
- DMA Controller on original PC
- DMA Controller in Figure 3-46 of Tanenbaum and Figure 4-19 of
the handout also have the following control lines:
-
MEM READ L and MEM WRITE L tell memory
to read or write what's on the bus.
-
TC is the terminal count that is asserted on last
cycle to reset ports interal state.
-
MARK is asserted every 128 bytes.
- Transfer request line 0 on the PC is used to control
dynamic refresh of the memory.
SKILL: You should understand the basic ideas of bus arbitration.
Revision Date: 4/22/97