CS 2734 Computer Organization II

Read pages 291-299 (Sections 12.1-12.4) of Paul

• Tanenbaum distinguishes interrupts which are asynchronous from traps which are synchronous and caused by program conditions such as divide by 0. The Sparc architects use the word trap to designate both. conditions such as divide by 0.

• Sparc recognizes traps listed in Table 12.1 on page 297 of Paul.

• Sparc processor state registers:
  • PSR - processor state register
    
    • condition codes
    • EF - floating point processor enabled,
    • PIL - processor interrupt level,
    • S - supervisor mode
    • PS - processor execution mode at last trap
    • ET - traps enabled
    • CWP - current window pointer

  • WIM - window invalid mask register has a single 1 bit indicating the last invalidated register set.
  • TBR - trap base register
    • TBA - starting address of trap address table.
    • tt - interrupt vector.

• Sparc trap handling:
  If ET bit is set, processor checks for traps between instruction cycles. When a trap with level greater than PIL occurs:
  • ET is cleared.
  • S bit of PSR is stored in the PS bit.
  • CWP is decremented so that handler can use local registers of next window.
  • pc, npc and psr are sotred in first three local registers.
  • pc = TBR and npc = TBR + 4.

• Return from trap:
  
  • CWP is incremented
  • Delated transfer of effect address of rett initiated by loading npc
  • S bit restored from PS.
  • ET set to 1.

• Sparc interrupt and trap priorities
  • Priority on the Sparc (in Table 12.1, a low numerical value for priority means a higher priority).
    • Traps have highest priority.
    • interrupt_level_15
    • interrupt_level_16 through interrupt_level_31

  • Priorities on the Sparc are handled by comparing the interrupt priority with the PIL field of the PSR. Notice that PIL is only 4 bits long.

  • An interrupt or trap cannot interrupt an ISR unless that ISR has reenabled ET.

• Priorities on Intel machines
  Intel machines have two interrupt levels maskable and nonmaskable. All I/O devices have to use the one maskable level. As a result Intel processors usually use a separate interrupt controller such as an 8259A (figure 3-38 of Tanenbaum).

Revision Date: 4/18/97 at 10:45am