CS 2734
Computer Organization II
Read pages 291-299 (Sections 12.1-12.4) of Paul
PSR - processor state registerEF - floating point processor enabled,
PIL - processor interrupt level,
S - supervisor mode
PS - processor execution mode at last trap
ET - traps enabled
CWP - current window pointer
WIM - window invalid mask register
has a single 1 bit indicating the last invalidated register set.
TBR - trap base register
TBA - starting address of trap address table.
tt - interrupt vector.
ET bit is set, processor checks for traps
between instruction cycles. When a trap with level greater
than PIL occurs:
ET is cleared.
S bit of PSR is stored in the
PS bit.
CWP is decremented so that handler can use
local registers of next window.
pc, npc and psr
are sotred in first three local registers.
pc = TBR and npc = TBR + 4.
rett
initiated by loading npc
S bit restored from PS.
ET set to 1.
interrupt_level_15
interrupt_level_16 through
interrupt_level_31
PIL field of the
PSR. Notice that PIL is only
4 bits long.
ET.
Revision Date: 4/18/97 at 10:45am