CS 2734 Computer Organization II

Read pages 307-313 (Sections 5.5.4 and 5.5.5) of Tanenbaum and pages 291-299 (Sections 12.1-12.4) of Paul

• Review: two methods for letting CPU know that an I/O is complete:
  • Polling - CPU tests the device status register.
  • Interrupt - the device sends a signal to the CPU.

• An interrupt is an asynchronous change in the flow of control caused by something external to the CPU.

• Hardware actions for handling an interrupt (simplified):
  • Device (controller) asserts interrupt line on system bus.
  • CPU recognizes that an interrupt has occurred as one step in its instruction cycle.
  • CPU asserts an interrupt acknowlege on the bus.
  • Device puts a small integer called interrupt vector on the bus.
  • CPU reads interrupt vector and stores it (usually in a special register).
  • CPU pushes PC and PSW (status registers like flag) onto stack.
  • CPU uses interrupt vector as an index into a table to start executing an ISR (interrupt service routine).

• Software actions for handling an interrupt (simplified):
  • ISR saves all registers (either on stack or in a special place).
  • ISR determines specific device that caused interrupt.
  • Service the device.
  • Restore all saved registers.
  • Execute a return from interrupt which restores the status register as well as the PC.

• Since an interrupt could occur at any time it must be completely transparent to any program executing on the machine.

• Tanenbaum distinguishes interrupts which are asynchronous from traps which are synchronous and caused by program conditions such as divide by 0. The Sparc architects use the word trap to designate both.

Revision Date: 4/18/97